This invention relates to delay-locked loops (DLLs) and, more particularly, to circuitry for eliminating false lock in DLLs.
A DLL may be used to provide delayed copies of a reference signal (e.g., a clock signal), which may be routed to digital circuit elements (e.g., flip-flops, registers, etc.). The DLL may include delay elements, which may be connected in series to create a delay line. When the total delay on the delay line is equal to one period of the reference signal, the DLL is considered to have acquired lock. The DLL detects for this by determining when the reference signal and the delay line output are edge-aligned. Once the DLL has acquired lock, the outputs of the individual delay elements may be used to provide the reference signal, with various amounts of delay, to digital circuit elements.
DLLs serve many useful purposes in digital systems. In one example, DLLs may be used in clock distribution networks to compensate for delays between a clock distribution source and a load. For example, if the clock distribution source is located at a distance from the load, the clock signal will not be received by the load instantaneously, i.e., there will be a delay in the time it takes to receive the clock signal. A DLL may be used to compensate for this delay by adding an additional delay to the transmitted clock signal such that the received clock signal is delayed, in total, by exactly one clock period from the transmitted clock signal. For example, if a clock signal is received 1 nanosecond after it is transmitted and the clock signal has a period of 4 nanoseconds, then a DLL may provide a delay of an additional 3 nanoseconds. In this approach, the transmitted clock signal and the received clock signal have no discernable difference.
In another example, DLLs may be used in subsampling systems. A DLL may produce signals of various phases to the subsampling system.
However, DLLs may also suffer from problems. One possible problem is that a DLL may acquire false lock and provide more delay than intended. Many DLLs assume that correct lock has been acquired when a reference signal is edge-aligned with the output of the delay line. In false lock, the output of the delay line is still edge-aligned with the reference signal. However, the delay line has more than one period of delay. For example, if a DLL has acquired correct lock, delay elements in a three-element delay line each provide a third of a period of delay. In another example, if the DLL has acquired false lock and the delay line has two periods of delay, each delay element provides two-thirds of a period of delay, instead of a third of a period of delay under correct lock. The additional delay in false lock may be undesirable. When false lock is not detected and is allowed to persist, outputs of digital circuit elements using DLL output signals may become skewed and further delayed themselves.